1. Field of the Invention
This invention relates to a semiconductor memory device such as a static RAM (random access memory) device, and more particularly to a high speed read-out function and a flash-clear function of a semiconductor memory device.
2. Description of the Prior Art
A semiconductor memory device such as a static RAM which has a high speed read-out function is already known and disclosed, for example, in Japanese Patent Publication No. 60 (1985)-44747, wherein high speed operation is attained by suitably controlling variable load means provided at terminal ends of bit lines (data lines).
A semiconductor device of the precharging type is also known wherein, upon selection of a word line, bit lines are brought into a floating state to reduce current flow into memory cells of the device and a quick change in potential is attained by driving transistors for the memory cells.
FIG. 1 shows a partial circuit configuration of an exemplary one of conventional memory devices (SRAMs) which employs such a precharging technique. In the memory device shown, a memory cell 11 is disposed between a pair of bit lines BL1 and BL2 via access transistors 12 and 13 the gates of which are connected to a word line WL. A pair of NMOS transistors 15 and 16 serving as load elements are provided at the terminal ends of the bit lines BL1 and BL2. A power source voltage Vcc is applied to the drains of the NMOS transistors 15 and 16. Another equalizing NMOS transistor 14 is disposed between the bit lines BL1 and BL2. Each of the NMOS transistors 14, 15 and 16 has a threshold voltage Vth(L) which is lower than that of ordinary NMOS transistors, and a precharge signal .PHI.b is supplied in common to the gates of the NMOS transistors 14, 15 and 16.
A further pair of NMOS transistors 17 and 18 are connected at the sources thereof to the bit lines BL1 and BL2, respectively. The gates and drains of the NMOS transistors 17 and 18 are connected in common to the power source voltage Vcc. The NMOS transistors 17 and 18 have an ordinary threshold voltage Vth.
The memory device having such a circuit configuration operates in the following manner. Referring to FIG. 2, an address signal tot he memory device transits at an instant t.sub.0, and a precharge signal .PHI.b rises at an instant t1 before a signal on the word line WL rises at an instant t3. As a result of such a rise of the precharge signal .PHI.b, the bit lines BL1 and BL2 are equalized via the NMOS transistor 14 and then the NMOS transistors 15 and 16 are turned on. Consequently, the potentials on the bit lines BL1 and BL2 are raised up to a level equal to Vcc-Vth(L). Thereupon, the potential difference between the gates and sources of the NMOS transistors 17 and 18 is decreased lower than the threshold voltage Vth to thereby turn off the NMOS transistors 17 and 18. Then at an instant t.sub.2, the precharge signal .PHI.b falls. Consequently, the NMOS transistors 14, 15 and 16 are all turned off to thereby place the bit lines BL1 and BL2 into a floating state. Then at the instant t.sub.3, the word line WL rises, and consequently the potential on one of the bit lines BL1 and BL2 is lowered by a driving transistor not shown in the memory cell 11. When the potential on the one bit line BL1 or BL2 is lowered below the level of Vcc-Vth, that one of the NMOS transistors 17 and 18 which is connected to the one bit line BL1 or BL2 is turned on so that the lower potential on the one bit line BL1 or BL2 is thereafter maintained at a constant level.
With the memory device described above, the NMOS transistors 15 and 16 have a threshold voltage Vth(L) which is lower than an ordinary threshold voltage Vth. Consequently, a high bit line potential can be attained upon precharging, and a sufficiently great difference signal can be produced between the two bit lines.
In a conventional memory device, however, NMOS transistors having a lower threshold voltage Vth(L) are used as load elements formed at the terminal ends of the bit lines BL1 and BL2. Accordingly, a step for lowering the threshold voltage is necessary in addition to the ordinary process, which eventually brings about an increase in production cost.
Furthermore, a random access memory device such as a static RAM device is equipped with a flash clear function. According to the function, when a single control signal is fed from an external circuit, either "0" or "1" is written into all of memory cells of the memory device at a time. Therefore, such a function is utilized for initializing the memory device for resetting or testing.
In a conventional random access memory device, the flash clear is executed simultaneously for an entire memory cell array of the memory device. This raises a problem that the current flow upon flash clearing presents a critically high peak value.
In fact, the storage capacity of a memory device has been increased significantly in recent years and a memory cell array is in a fair way to a large scale. If such a large scale memory cell array is cleared at one time, the peak electric current flow in the memory device amounts to an extremely high value. An increase of such a peak current will naturally cause considerable variation in the level of the power supply line or the ground line serving the memory device. Accordingly, there is the possibility that noises may be produced or wires in the chip may be fused to cause destruction of the inner structure of the chip or destruction of an appliance in which the memory device is used.
In view of such circumstances, several inventions have been made wherein a memory cell array is segmented into a plurality of memory cell groups to which a batch writing operation is made successively at different timings. One of such inventions is disclosed in Japanese Patent Application No. 62 (1987)-290408 filed by the applicant of the present patent application.
The memory device is shown in a block diagram of FIG. 3(A). Referring to FIG. 3(A), the memory device shown includes a starting circuit a which generates a starting signal in response to a starting instruction signal fed thereto. The memory device further includes a plurality of flash clear circuits b1, b2, b3 . . . and bn which are provided in a corresponding relationship to a plurality of memory cell groups c1, c2, c3, . . . and cn which are formed by segmenting a memory cell array into n sections. The starting signal thus generated from the starting circuit a is supplied to the first flash-clear circuit b1, which thus sends a flash clearing signal FC1 to the first memory cell group c1 for flash-clearing of the same. Meanwhile, the flash-clear circuit b1 delays the starting signal received from the starting circuit a and forwards the thus delayed signal to the second flash-clear circuit b2. In response to the delayed starting signal from the first flash-clear circuit b1, the second flash-clear circuit b2 delivers a flash clearing signal FC2 to the memory cell group c2 for flash-clearing of the same. Meanwhile, the second flash-clear circuit b2 also delays the received starting signal and forwards the delayed signal to the third flash-clear circuit b3. Thus, the memory cells of the memory cell groups c1 to cn are successively flash-cleared in accordance with a predetermined order as seen from the time chart of FIG. 3(H). The memory device having such a construction as described above presents a significantly low value of peak current flow therein upon flash-clearing because the memory cell groups therein are flash-cleared at different timings.
In such a memory device as shown in FIG. 3(A), however, a separate flash-clear circuit b must be provided for each memory cell group c1 to cn. Accordingly, the memory device includes a significantly large number of flash-clear circuits b, which leads to a problem that the area of the chip of the memory device is significantly great.